Parallel Multipler

The PMU accepts two serial inputs as multiplicand and multiplier in one word time, produces their properly rounded product by means of a parallel algorithm in one more word time, and shifts the product out in the next word time while inputs for the next operation are simultaneously shifted in. The parallel multiply algorithm used is called Booth’s Algorithm (1). Two’s complement representation is used for negative numbers. The PMU consists of three registers, the Multiplicand (M), the Multiplier (R), and the Product (P). The 20-bit parallel multiply is accomplished in one word time of 106.6 microseconds.

(1) CHU, YOAHAN, “Digital Computer Design Fundamentals,” 1962, Mc Graw Hill, Inc., page 32

Parallel Multiplier F-14

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